A known buffer circuit used in a large-scale integration consists of a series combination of two n-channel MOS (metal-oxide-semiconductor) field effect transistors which is connected between a positive voltage source producing a positive high voltage level V.sub.CC and the ground. The two MOS field effect transistors have respective gate electrodes applied with complementary drive signals, respectively, and each of the complementary drive signals swings its voltage level between the positive high voltage level V.sub.CC and the ground voltage level. With the complementary drive signals, the MOS transistors are complementarily switched between their on-states and their off-states. The prior-art buffer circuit has an output node between the two MOS field effect transistors and the output node has either high or low voltage level depending upon the voltage levels of the drive signals. Namely, one of the MOS field effect transistors turns on to provide a conduction path from the ground to the output node and the other of the MOS field effect transistors turns off to block a conduction path from the positive voltage source to the output node, then the output node has the low voltage level approximately equal to the ground voltage level. On the other hand, when the two MOS field effect transistors are complementarily switched from the on-state to off-state and vice versa, respectively, the conduction path from the positive voltage source to the output node is established but the conduction path from the ground to the output node is blocked. This results in that the output node has the high voltage level V.sub.OH given by EQU V.sub.OH =V.sub.CC -V.sub.TH -V.sub.IOUT
where V.sub.TH is the threshold voltage of the MOS field effect transistor including the influence of a back-gate bias voltage and V.sub.IOUT is the value of a voltage drop due to the flow of the output current.
When the dimensions of the transistor is reduced for improving the integration density, the threshold voltage VTH of the MOS field effect transistor is increased in value under the influence of back-gate bias effect. This is because of the fact that the back-gate bias effect deteriorates when ion implantation is carried out with increased energy for improvement of the breakdown voltage. A problem is encountered in the prior-art buffer circuit in reduction of voltage amplitude at the output node. To avoid such a problem, the ion implantation to the MOS field effect transistors forming part of the buffer circuit be carried out separately from the ion implantation to the other component MOS field effect transistors. This results in increasing in lithographic process, then irregularity of the transistor's characteristics tends to take place.